A static random access memory (SRAM) is advantageous in that it does not need to be dynamically updated as done in a dynamic random access memory (DRAM) and is fast in speed. Such a SRAM is a block, which occupies most of an area and a consumed power of a general integrated circuit, like a communication module, an image processor and others. Accordingly, a bit cell of the SRAM is designed to be minimized so as to increase a degree of the integration, and a semiconductor process in this regard has been also miniaturized. As a result, stability of a semiconductor circuit has been deteriorated more and more, and the deterioration has been considered a serious problem in the latest process for transistors such as a fin field effect transistor (finFET).
Meanwhile, a structure of a general SRAM cell includes two (2) invertors, which are commonly formed in four (4) complementary metal-oxide semiconductor field-effect transistors (MOSFETs) and cross-coupled to one another. The cross-coupled invertors form a basic storage element with two (2) stable states. In this case, the two (2) stable states refer to ‘0’ and ‘1,’ which are complementary binary values. The SRAM cell includes two (2) additional transistors, which are named access transistors. In this case, the access transistors perform controlling access to the storage element during reading and writing operations.
FIG. 1 is an example for a 6T SRAM cell in accordance with a conventional technology.
The 6T SRAM cell includes six (6) transistors. As shown in FIG. 1, the 6T SRAM cell may be divided into three (3) sections, i.e., a pull-up PMOS 20, a pass-gate NMOS 10 and a pull-down NMOS 30, and nodes between the pass-gate NMOSs 10 connected to the pull-up PMOSs 20 and the pull-down NMOSs 30 hold complementary binary values.
In the writing operation of the SRAM cell, a positive voltage is applied to a word line (WL) to activate the word line, so that the pass-gate NMOSs 10 transfer values on the complementary bit lines into the SRAM bit cell. In addition, in the reading operation of the SRAM cell, the word line is activated in the state that each of the bit lines is pre-charged and held to have a pre-defined value (that is, in the pre-charge state), so that one of the bit lines is discharged by the complementary values stored within the SRAM bit cell.
Meanwhile, in order to improve an operation margin of the reading operation in the SRAM, it is necessary to make the pull-down NMOS 30 stronger than the pass-gate PMOS 10. However, since the strength of the pass-gate NMOS 10 contradicts with the operation margin of the reading and writing operations, there is a limit in improving the stability of the SRAM by adjusting the size of the bit cell. To solve this problem, the latest processes are necessarily using an assist circuit technology, which adds a separate circuit to a peripheral circuit of a memory.
The assist circuit technology may be classified into a method of controlling a voltage to be applied to a power supply of a memory bit cell, a method of controlling a voltage to be applied to a word line, or a method of controlling a voltage to be applied to a bit line. In this case, the margin of the reading operation can be improved by using a method of increasing a voltage to be applied to be a bit cell or by reducing the strength of the pass-gate NMOS 10 or increasing the strength of the pull-down NMOS 30, or through a method of lowering a voltage to be applied to a word line or a bit line. To the contrary, the margin of the writing operation can be improved by using a method of reducing a voltage to be applied to a bit cell by increasing the strength of the pass-gate NMOS 10 or reducing the strength of the pull-up PMOS 20, or through a method of increasing a voltage to be applied to a word line or a bit line.
FIG. 2 and FIG. 3 illustrate an assist circuit of a SRAM cell in accordance with a conventional technology.
In case of the form, in which the SRAM cells are dense in a cache, like a microprocessor, a power grid may be easily formed in the inside of the chip through an external power supply. However, where the SRAM is distributed in the whole chip like a system on chip (SoC), there is a problem since it is difficult to use one or more power supply sources. Accordingly, the conventionally suggested SRAM assist circuit technique generates necessary voltages such as a over-driven voltage or a under-driven voltage, in addition to a memory supply voltage, from only one power supply source through a voltage divider or a voltage regulator illustrated in FIG. 2, in addition to an additional power supply source applied from the outside. However, as a short circuit current occurs in the voltage divider or the voltage regulator, a consumed power of the voltage divider or the voltage regulator occupies most of the power consumed in the whole memory.
In addition, FIG. 3 illustrates a multiport resistor file including a multi-bit line 60 and a multi-word line 70, which are used for a high-speed parallel processor. The multiport resistor file improves the margin of the reading operation and reduces the margin of the writing operation upon use of an over-driven voltage. To the contrary, the multiport resistor file reduces the margin of the reading operation and improves the margin of the writing operation upon use of a under-driven voltage. However, the multiport resistor file that operates as described above has many restrictions in applying the conventional SRAM assist circuit techniques. For example, where the reading and writing operations are connected to an identical array, it causes deterioration of stability and performance of two (2) bit cells.
In this regard, Korean Patent Application Publication No. 2010-0101008 (Title of Invention: Semiconductor Memory Device) describes a semiconductor memory device including a SRAM, which realizes a small SRAM cell in a CMOS-type 6T-SRAM using SGT, and simultaneously, has a sufficient operation margin.
However, since this technology does not use the assist circuit technique like the conventional technology described in FIG. 1 above, there is a limit in improving the stability of the SRAM by adjusting a size of a bit cell.